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SI9120
Vishay Siliconix
Universal Input Switchmode Controller
FEATURES
D 10- to 450-V Input Range D Current-Mode Control D 125-mA Output Drive D Internal Start-Up Circuit D Internal Oscillator (1 MHz) D SHUTDOWN and RESET
DESCRIPTION
The SI9120 is a BiC/DMOS integrated circuit designed for use in low-power, high-efficiency off-line power supplies. High-voltage DMOS inputs allow the controller to work over a wide range of input voltages (10- to 450-VDC). Current-mode PWM control circuitry is implemented in CMOS to reduce quiescent current to less than 1.5 mA. A CMOS output driver provides high-speed switching for MOSFET devices with gate charge, Qg, up to 25 nC, enough to supply 30 W of output power at 100 kHz. These devices, when combined with an output MOSFET and transformer, can be used to implement single-ended power converter topologies (i.e., flyback and forward). The SI9120 is available in both standard and lead (Pb)-free 16-pin plastic DIP and SOIC packages which are specified to operate over the industrial temperature range of -40 _C to 85 _C.
FUNCTIONAL BLOCK DIAGRAM
OSC IN 9 OSC OUT 8
FB 15
COMP 14 Error Amplifier
DISCHARGE 10
OSC 2V - + + - 1.2 V C/L Comparator Clock (1/2 fOSC) R Q S
VREF
11
- + 4 V (1%) Ref Gen
To VCC
Current-Mode Comparator
5 6
OUTPUT -VIN
BIAS VCC +VIN
16
Current Sources
7 1
To Internal Circuits
4 VCC 12 13
SENSE
- 8.1 V - + 8.6 V Pre-Regulator/Start-Up +
Undervoltage Comparator Q
S R
SHUTDOWN RESET
Applications information, see AN707 and AN708. Document Number: 70006 S-42042--Rev. H, 15-Nov-04 www.vishay.com
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SI9120
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to -VIN (Note: VCC < +VIN + 0.3 V) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 V Logic Inputs (RESET SHUTDOWN, OSC IN, OSC OUT) . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Linear Input (FEEDBACK, SENSE, BIAS, VREF) . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . 5 mAa Continuous Output Current (Source or Sink) . . . . . . . . . . . . . . . . . . . 125 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150_C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85_C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (Package)b 16-Pin Plastic DIP (J Suffix)c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 mW 16-Pin SOIC (Y Suffix)d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (QJA) 16-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167_C/W 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140_C/W Notes a. Continuous current may be limited by the applications maximum input voltage and the package power dissipation. b. Device mounted with all leads soldered or welded to PC board. c. Derate 6 mW/_C above 25_C. d. Derate 7.2 mW/_C above 25_C.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Voltages Referenced to -VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 V to 13.5 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 450 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kW to 1 MW Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC - 3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
SPECIFICATIONSa
Specific Test Conditions Parameter Reference
Output Voltage Output Impedancee Short Circuit Current Temperature Stabilitye VR ZOUT ISREF TREF VREF = -VIN OSC IN = - VIN (OSC Disabled) RL = 10 MW Room Full Room Room Full 3.88 3.82 15 70 4.0 30 100 0.5 4.12 4.14 45 130 1.0 V kW mA mV/_C DISCHARGE = -VIN = 0 V, VCC = 10 V +VIN = 300 V RBIAS = 390 kW, ROSC = 330 kW LIMITS D Suffix -40 to 85_C TEMPB MINC TYPD MAXC
Symbol
Unit
Oscillator
Maximum Frequencye fMAX ROSC = 0 CSTRAY Pin 9 v 5 pF ROSC = 330 kW CSTRAY Pin 9 v 5 pF ROSC = 150 kW Df/f = f(13.5 V) - f(9.5 V) / f(9.5 V) Room Room Room Room Full 1 80 160 3 100 200 10 200 120 kHz 240 15 500 % ppm/_C MHz
Initial Accuracy Voltage Stability Temperature Coefficiente
fOSC Df/f TOSC
Error Amplifier
Feedback Input Voltage Input BIAS Current Input OFFSET Voltage Open Loop Voltage Gaine Unity Gain Bandwidthe www.vishay.com VFB IFB VOS AVOL BW FB Tied to COMP OSC IN = - VIN (OSC Disabled) OSC IN = - VIN, VFB = 4 V OSC IN = - VIN OSC IN = - VIN OSC IN = - VIN Room Room Room Room Room 60 1.0 3.92 25 "15 80 1.5 4.08 500 "40 V nA mV dB MHz
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Document Number: 70006 S-42042--Rev. H, 15-Nov-04
SI9120
Vishay Siliconix
SPECIFICATIONSa
Specific Test Conditions Parameter Error Amplifier (Cont'd)
Dynamic Output Impedancee Output Current Power Supply Rejection ZOUT IOUT PSRR Error Amp configured for 60 dB gain Source VFB = 3.4 V Sink VFB = 4.5 V 9.5 V v VCC v 13.5 V Room Room Room Room 0.12 50 1000 -2.0 0.15 70 2000 -1.4 W mA dB DISCHARGE = -VIN = 0 V, VCC = 10 V +VIN = 300 V RBIAS = 390 kW, ROSC = 330 kW LIMITS D Suffix -40 to 85_C TEMPB MINC TYPD MAXC
Symbol
Unit
Current Limit
Threshold Voltage Delay to Outpute VSOURCE td VFB = 0 V VSENSE = 1.5 V, See Figure 1 Room Room 1.0 1.2 100 1.4 150 V ns
Pre-Regulator/Start-Up
Input Voltage Input Leakage Current VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG -VUVLO +VIN +IIN VREG VUVLO VDELTA IIN = 10 mA VCC w 9.4 V IPRE-REGULATOR = 10 mA Room Room Room Room Room 7.8 7.0 0.3 8.6 8.1 0.6 450 10 9.4 8.9 V V mA
Supply
Supply Current Bias Current ICC IBIAS CL = 500 pF at Pin 5 Room Room 10 0.85 15 1.5 20 mA mA
Logic
SHUTDOWN Delaye SHUTDOWN Pulse Widthe RESET Pulse Widthe Latching Pulse Width SHUTDOWN and RESET Lowe Input Low Voltage Input High Voltage Input Current Input Voltage High Input Current Input Voltage Low tSD tSW tRW tLW VIL VIH IIH IIL VIN = 10 V VIN = 0 V See Figure 3 CL = 500 pF, VSENSE = -VIN See Figure 2 Room Room Room Room Room Room Room Room -35 8.0 1 -25 5 50 50 25 2.0 V mA 50 100 ns
Output
Output High Voltage Output Low Voltage Output Resistance Rise Timee Fall Timee VOH VOL ROUT tr tf IOUT = -10 mA IOUT = 10 mA IOUT = 10 mA, Source or Sink CL = 500 pF Room Full Room Full Room Full Room Room 40 20 25 40 75 9.7 9.5 0.3 0.5 30 50 75 V
W ns
Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25_C, Cold and Hot = as determined by the operating temperature suffix. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. e. Guaranteed by design, not subject to production test. a. 250 V v +VIN 380 V place a 10-kW, 1/4-W resistor in series with a +VIN (Pin1). 380 V v +VIN 450 V place a 15-kW, 1/4-W resistor in series with a +VIN (Pin1). Connect a 0.01-mfd capacitor between +VIN (Pin 1) and -VIN (Pin 6).
Document Number: 70006 S-42042--Rev. H, 15-Nov-04
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SI9120
Vishay Siliconix
TIMING WAVEFORMS
SENSE 0 VCC OUTPUT 0 -
1.5 V - 50% td
tr v 10 ns
VCC SHUTDOWN 0 VCC OUTPUT 0
50% - tSD
tf v 10 ns
90%
90% -
FIGURE 1.
FIGURE 2.
VCC SHUTDOWN 0 VCC RESET 0 50% - 50% -
tSW 50% tLW 50% tRW 50% tr, tf v 10 ns
FIGURE 3.
TYPICAL CHARACTERISTICS
Output Switching Frequency vs. Oscillator Resistance
1M
f OUT (Hz)
100 k
10 k 10 k 100 k rOSC - Oscillator Resistance (W) 1M
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Document Number: 70006 S-42042--Rev. H, 15-Nov-04
SI9120
Vishay Siliconix
PIN CONFIGURATIONS AND ORDERING INFORMATION
Dual-In-Line
+VIN NC* NC* SENSE OUTPUT -VIN VCC OSC OUT 1 2 3 4 5 6 7 8 Top View 16 15 14 13 12 11 10 9 BIAS FB COMP RESET SHUTDOWN VREF DISCHARGE OSC IN SENSE OUTPUT -VIN VCC OSC OUT 4 5 6 7 8 +VIN 1
SOIC
16 15 14 13 12 11 10 9 BIAS FB COMP RESET SHUTDOWN VREF DISCHARGE OSC IN
Top View Note: Pins 2 and 3 are removed
ORDERING INFORMATION
Part Number
SI9120DY SI9120DY-T1 SI9120DY-T1--E3 SI9120DJ SI9120DJ--E3 -40 to 85_C PDIP-16 PDIP 16 SOIC-16
Temperature Range
Package
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the SI9120 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, +VIN (pin 1) will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET which is connected between +VIN and VCC (pin 7). This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is disabled when VCC exceeds 8.6 V. If VCC is not forced to exceed the 8.6-V threshold, then VCC will be regulated to a nominal value of 8.6 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output driver disabled until VCC exceeds the undervoltage lockout threshold (typically 8.1 V). This guarantees that the
Document Number: 70006 S-42042--Rev. H, 15-Nov-04
control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will be at least 300 mV less than the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. Note: When driving large MOSFETs at high frequency without a bootstrap VCC supply, power dissipation in the pre-regulator may exceed the power rating of the IC package. For operation of +VIN > 250 V, a 10-kW, 1/4-W resistor should be placed in series with +VIN (Pin 1). For +VIN > 380 V, a 15-kW, 1/4-W resistor is recommended.
BIAS To properly set the bias for the SI9120, a 390-kW resistor should be tied from BIAS (pin 16) to -VIN (pin 6). This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15 mA.
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SI9120
Vishay Siliconix
DETAILED DESCRIPTION (CONT'D)
Reference Section The reference section of the SI9120 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the SI9120 brings the output of the error amplifier (which is configured for unity gain during trimming) to within "2% of 4 V. This compensates for input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. SHUTDOWN and RESET SHUTDOWN (pin 12) and RESET (pin 13) are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET. SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. See Table TABLE 1.
Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time.
Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" compensation. A MOS differential input stage provides for high input impedance. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground.
TABLE 1. TRUTH TABLE FOR SHUTDOWN AND RESET PINS
SHUTDOWN
H H L L H L L
RESET
H
OUTPUT
Normal Operation Normal Operation (No Change) Off (Not Latched) Off (Latched) Off (Latched--No Change)
Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Typical Characteristics for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to -VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to v 50% by locking the switching frequency to one half of the oscillator frequency. Output Driver The push-pull driver output has a typical on-resistance of 20-W maximum switching times are specified at 75 ns for a 500-pF load. This is sufficient to directly drive MOSFETs such as the IRF820, BUZ78 or BUZ80. Larger devices can be driven, but switching times will be longer, resulting in higher switching losses.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70006. www.vishay.com Document Number: 70006 S-42042--Rev. H, 15-Nov-04
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